The invention relates to a semiconductor device comprising a semiconductor body provided with a circuit element at the area of an opening in an insulating layer present on a surface of the semiconductor body and an interconnection pattern located at least in part on the insulating layer.
The invention further relates to a method of manufacturing such a semiconductor device.
The circuit element generally forms part of an integrated circuit and can be a (bipolar or unipolar) transistor as well as, for example, a resistor.
A semiconductor device of the kind mentioned in the preamble having a MOS transistor as circuit element is known from U.S. Pat. No. 3,699,646. This device comprises for a source or drain zone of the MOS transistor a pattern of silicon which is provided on a layer of thick oxide (field oxide). At the area of the transistor there is provided an opening in the field oxide within which the silicon pattern extends. At areas at which the pattern contacts a source or drain zone, this pattern is directly applied to the semiconductor body. At other areas, the (polycrystalline) silicon acts as a gate contact and is separated from the semiconductor body by a layer of thin oxide (gate oxide).
In the design of semiconductor devices, increasingly higher integration densities are aimed at, on the one hand in order to be able to realize a maximum number of functions on an equal surface area, and on the other hand in order to be able to attain higher yields in the manufacture due to the smaller surface area required for such a circuit arrangement.
In the transistor according to the U.S. Pat. No. 3,699,646, the minimum dimension of, for example, the source zone of the transistor is determined by the size of a diffusion window having dimensions dependent upon two tolerances. First, it is necessary for a satisfactory contacting that the material of the interconnection pattern covers the semiconductor surface over a minimum distance. In order to be sure of this, the relative tolerance of the masks defining the interconnection pattern and the opening in the field oxide, respectively, have to be taken into account.
Furthermore the size of the diffusion window is dependent upon the distance between this contacting area and the gate contact. During the manufacture of the transistor, an electrode of polycrystalline silicon is provided for the gate contact on a thin layer of oxide, which is then removed, the electrode being used as a mask. The distance between the contacting area of the source zone and the gate contact therefore depends in the first instance on the absolute tolerance of the mask defining the interconnection pattern because the contacts are formed therefrom.
When the size of the transistor is reduced, however, another tolerance will play a part. In order to ensure that, when the layer of thin oxide is removed, the gate electrode indeed covers this layer, the relative tolerance of the mask defining the thin oxide with respect to the mask defining the interconnection pattern has to be taken into account.
The said tolerances set limits to the size of the diffusion openings and hence to the dimensions of the transistor.
Furthermore, during the manufacture of semiconductor devices attempts are made to arrange different transistors, such as bipolar transistors and MOS transistors, in the same semiconductor body. In the said U.S. Patent mentioned above, one type of impurity is used for doping both the polycrystalline silicon and the source and drain zones of MOS transistors. The device shown thus comprises only one kind of transistor, in this case MOS- transistors of the same type (p-type or n-type).